RF synthesizers are used to provide clock signals to one or more system circuits based on a high frequency master clock signal from a voltage controlled oscillator (VCO) or other clock source. Fixed frequency dividers or channel dividers are used to divide the VCO output signal to generate lower frequency clock signals. New applications demand higher clock speeds where the VCO input frequency can exceed 10 GHz. In addition, many RF synthesizer applications require low noise operation, particularly low far-off phase noise performance of the frequency divider circuit following the VCO. In conventional designs, fixed frequency divider circuitry is a primary contributor to far-off phase noise, and extending operation to higher VCO input frequencies worsens phase errors, particularly for large division ratios needed to support both high and low frequency circuits in a given system. The divider circuit can be segmented into multiple cascaded divider stages, but timing specifications become critical when operating with a higher frequency input clock signals, such as 10 GHz. To meet stringent timing requirements, intervening resampling latches or flip-flops can be added to resample the divided clock signals with the input clock signal. However, the extra resampling flip-flops consume additional power. Thus, operating conventional divider circuits at increased input frequencies generally increases far-off phase noise and also leads to increased power consumption.